As semiconductor manufacturing technology advances to smaller and smaller feature sizes, porous low dielectric constant (low-k) integration with Copper interconnect technology has been widely evaluated. Interconnect delay becomes a significant performance barrier for high-speed signal conduction. The use of dielectric materials with a lower dielectric constant can significantly improve performance measures by reducing signal propagation time delay, cross talk, and power consumption in semiconductor devices having a multilevel interconnect architecture. The most-used dielectric material for semiconductor fabrication has been silicon oxide (SiO2), which has a dielectric constant in the range of k=3.9 to 4.5, depending on its method of formation. Dielectric materials with k less than 3.9 are classified as low-k dielectrics. Some low-k dielectrics are organosilicates formed by doping silicon oxide with carbon-containing compounds.
A dual-damascene interconnect structure requires only a single metal deposition step to simultaneously form metal lines and metal in vias. In other words, both trenches and vias are formed in a single dielectric layer. The vias and trenches are formed by using two lithography operations. A via then trench prior approach for fabricating dual-damascene interconnect structures is illustrated in FIGS. 1A, 1B, and 1C. In FIG. 1A, a via masking layer is disposed on a hard mask layer, which is disposed on a low-k dielectric layer, which is disposed on a etch stop layer, which is disposed partially on an oxide layer and partially on a Copper metal layer. Vias are etched in the openings of the via masking layer and then filled with an organic planarizing layer. The trench hard mask layer is then deposited followed by trench lithography as illustrated in FIG. 1B. Trenches are then etched followed by strip operations resulting in the interconnect structure illustrated in FIG. 1C. The vias and trenches are then filled with metal.
This prior approach for forming dual-damascene interconnect structures has various problems. The via etch has a high aspect ratio making this a difficult etch in terms of obtaining vertical sidewalls and uniform via size across a wafer in a repeatable manner for a manufacturing process. After the via etch and strip, the vias are exposed to several etch processes including the trench etch, an organic planarizing layer strip, and a etch stop layer etch. These subsequent etches can alter the shape of profile of the vias. Also, the low-k dielectric layer that forms the via sidewalls is modified with a resulting increase in the dielectric constant and increase in interconnect delay. During the trench etch, the corners of the vias are exposed and rounded. This negatively impacts the via contact resistance and interconnect delay within a die as well as across wafer uniformity. The etch stop layer needs to be thick enough to provide barrier properties such as prevent Copper diffusion from the metal layer into the low-k dielectric layer and also preventing Copper oxidation. The etch stop layer has a dielectric constant greater than the low-k dielectric layer and thus increases the effective dielectric constant of the film layers in combination.
FIG. 2 illustrates an example of a low quality etch front including pitting/voiding, surface roughness, and microtrenching near the edges of features. The mechanism of these defects may relate to the trench etch being performed simultaneously with the organic layer etch as illustrated in FIGS. 1B and 1C.
In a trench-first prior approach, the trench patterns are defined in a interlayer dielectric first. That is, after spinning on the resist, the trench-pattern-mask is used to expose the resist. The trench is then produced by etching the dielectric down to the embedded etch-stop layer. After the trench-etching process, the first resist layer is stripped. A second resist layer is then spun on, and the via-pattern-mask, which is aligned to the trench that was previously etech, is used to create openings in this resist layer. The resist protects the other parts of the wafer surface (including the etched regions of the trenches) so that the vias can be etched without further etching the dielectric in the trenches.
However, this prior approach of the trench-first sequence suffers from the fact that the vias must be patterned after the trench etch. That is, since resist is applied as a liquid onto the wafer surface, it fills recessed regions first. Hence, the top surface of the resist is planar. This means that the regions of resist over the damascene trenches are quite thick. Resolving fine features in thick resist is harder than in thinner resists. For smaller features the process latitude becomes too small for this to be a practical manufacturing process.